ESD和闩锁测试

EAG Laboratories is an industry leader in ESD (Electrostatic Discharge) testing and latch-up testing. Our experienced engineering team leverages industry-leading expertise and years of hands-on experience, combined with cutting-edge semiconductor technology, circuit design, and device physics, to optimize clients' ESD and latch-up performance. When you choose EAG, you collaborate with renowned experts in ESD and latch-up testing. We are committed to providing clients with the latest testing methodologies, along with technical interpretation of test data and accurate evaluation of results. Additionally, EAG's ITAR-compliant testing laboratories ensure protection for our aerospace and defense clients.

Our in-house PCB team can also rapidly create custom ESD fixtures to accelerate your path to results. Furthermore, EAG's ESD team is part of a larger service organization that grants clients seamless access to world-class capabilities in failure analysis, environmental/reliability testing, FIB circuit editing, electron microscopy, and ATE testing services.

With six Thermo Fisher Scientific Orion CDM machines, EAG Laboratories boasts the highest capacity and most advanced equipment for Charged Device Model (CDM) testing. Our ISO 9001:2015-certified full-service laboratory also offers failure analysis, advanced microscopy, and materials testing to identify root causes of ESD failures.

HBM, MM, CDM Testing

Applicable HBM Standards:

• JEDEC: JS-001-2017 and JESD22-A114 (superseded by JS-001-2017)

• Department of Defense: MIL-STD-883, Method 3015.7

• Automotive Electronics Council: AEC-Q100-002 and AEC-Q101-001 (based on JS-001-2017)

• ESD Association: ESD STM 5.1-1998 (superseded by JS-001-2017)

Applicable CDM Standards:

• JEDEC: JS-002-2018 and JESD22-C101 (superseded by JS-002-2018)

• Automotive Electronics Council: AEC-Q100-011 and AEC-Q101-005 (based on JS-002-2018)

• ESD Association: ESDA STM 5.3.1-1999 (superseded by JS-002-2018)

Applicable MM Standards:

• JEDEC: JESD22-A115 (phased out by JEDEC but still available)

• Automotive Electronics Council: AEC-Q100-003 and AEC-Q101-002 (phased out by AEC but still available)

• ESD Association: ESD STM 5.2-1999 (phased out by ESDA but still available)

Latch-Up Testing

While latch-up testing is performed on the same automated testers as ESD testing, the tests are fundamentally different. ESD testing is not conducted under bias. Latch-up testing is performed with the DUT powered, and signals are applied to place the device in a stable low-current configuration. Dedicated ESD/LU worksheets are used to configure automated testers such as the Thermo Scientific Mk2 or Mk4. Each tester channel has unique capabilities and can be programmed as a power supply, signal pin, or vector pin.

The goal of IC latch-up testing is to trigger and monitor potential latch-up events where stress pulses activate parasitic transistor structures in CMOS or Bi-CMOS process technologies. Latch-up testing essentially revolves around the chip's physical layout, the positioning of circuit blocks relative to each other, and how unintended charges are dissipated from physical components in semiconductor materials.

Latch-up testing is performed according to the current version of the JEDEC latch-up standard but can also be conducted based on prior versions of JESD78. Testing can be performed at client-specified ambient temperatures ranging from 25°C to 125°C. Due to the many variables involved, latch-up testing is quoted on a case-by-case basis, accounting for the estimated engineering time to develop the test plan, machine time for execution, and the reporting requested by the client.

Applicable LU Standards:

• JEDEC: JESD78E

• Automotive Electronics Council: AEC-Q100-004 (based on JESD78E)

Transmission Line Pulse (TLP) Testing

Transmission Line Pulse (TLP) testing is a method used to characterize electrostatic discharge (ESD) protection structures in semiconductors. In TLP testing, high-current pulses are sequentially applied to the pin under test (PUT) through a coaxial cable of specified length at increasing levels. The applied pulses have current amplitudes and durations representative of Human Body Model (HBM) ESD/LU worksheet event simulations (or, for Very Fast TLP (VF-TLP), Charged Device Model (CDM) events). Incident and reflected pulses are evaluated, and a voltage-current (VI) curve is plotted to describe the ESD protection structure's response to the applied TLP stress. TLP testing is unique because the current pulses can reach magnitudes of amperes, and the results can reveal the ESD protection structure's turn-on, snapback, and holding characteristics.

TLP testing is valuable in two critical ways. First, TLP can characterize input/output (I/O) pad cells on test chips for new process technologies and intellectual property (IP). It is highly useful for developing simulation parameters and qualitatively comparing the relative merits of different ESD protection schemes for innovative pad cell designs. Second, TLP can serve as an electrical failure analysis tool, often used in conjunction with traditional standards-based component ESD testing.

TLP testing is performed according to the ESDA TLP test method ESDA SP5.5-2003. TLP services are quoted individually based on the required testing scope, estimated engineering time for execution, and the reporting requested by the client.

Applicable TLP Standards:

• ESDA SP5.5-2003 (ESD Association)